What Is HBM? High-Bandwidth Memory vs DRAM, HBM3E and HBM4

HBM, short for high-bandwidth memory, is the memory packed next to the chips that train and run AI models. It is not a new kind of memory cell: it is DRAM, the same working memory found in phones and PCs, built in a different shape. Its three big suppliers are SK hynix, Samsung Electronics and Micron.

What is HBM made of?

A stack of thin DRAM chips sitting on a base chip. Micron describes it this way: “HBM stacks multiple DRAM dies vertically atop an optional base die. They are interconnected using thousands of through-silicon vias (TSVs) and microbumps.” A through-silicon via is a tiny vertical wire that runs straight through a chip, so data can “flow directly through the silicon stack instead of traveling around the edges of chips,” in Micron’s words.

Micron lists three kinds of chips in each stack: DRAM dies with TSVs, a thicker top DRAM die without them that “provides memory as well as structural integrity,” and a logic die at the bottom “with TSVs to interface with the system.” Samsung says the base die matters more with each generation; for HBM4 it builds that die on its own 4-nanometer foundry process.

Stacks come in different heights. Samsung says HBM “commonly” comes in 4-high, 8-high and 12-high configurations, and its HBM4E reaches 16-high. More layers add capacity but, as Samsung notes, “also increase thermal and manufacturing challenges.” The layers are bonded and protected with special processes; SK hynix uses one it calls MR-MUF, which injects a liquid protective material between the chips and hardens it.

How is HBM different from ordinary DRAM?

Mainly in its shape and its connection to the processor. “Unlike traditional memory, where chips sit next to one another, HBM stacks DRAM dies on top of each other,” Micron says, and the stack sits right beside the processor inside the same package. That lets it use a very wide connection: 1,024 data lines per stack for HBM3 and HBM3E and 2,048 for HBM4, according to Samsung’s product pages. More lines working at once move far more data per second.

The two are not rivals. Micron says HBM “works alongside other memory types rather than replacing them. For example, in modern systems, CPUs use LPDDR5 or DDR5 to coordinate the system while GPUs use HBM4 for demanding math.” The price of the speed is complexity: Micron calls HBM “one of the more challenging memory products to produce.”

How do HBM3, HBM3E and HBM4 compare?

Each generation has widened the interface, raised the speed per pin, or both. Bandwidth per stack is roughly the number of data lines times the speed per line, divided by eight to convert bits to bytes.

Generation	Data lines per stack	Speed per pin	Bandwidth per stack	Capacity per stack
HBM3 (Samsung)	1,024	6.4 Gbps	up to 819 GB/s	16 or 24 GB
HBM3E (Samsung)	1,024	up to 9.2 Gbps	up to 1,180 GB/s	24 GB (8-high), 36 GB (12-high)
HBM4 (Samsung)	2,048	up to 13 Gbps	up to 3.3 TB/s	36 GB (12-high)
HBM4E (Samsung)	2,048	up to 16 Gbps	4 TB/s	up to 64 GB (16-high)

The industry standard is set by JEDEC, the semiconductor standards body. SK hynix puts the JEDEC standard operating speed for HBM4 at 8 Gbps per pin, and the makers ship faster parts: SK hynix says its HBM4 runs at over 10 Gbps, and Samsung says its mass-produced HBM4 runs at a consistent 11.7 Gbps, “exceeding the industry standard of 8Gbps by approximately 46%,” and is capable of 13 Gbps. Micron’s HBM4 runs at more than 11 Gbps for more than 2.8 TB/s per stack.

Capacity does not always rise with a new generation. Micron points out that a 12-high HBM4 stack “provides 36GB of memory capacity per stack (the same as the previous generation)” but more than twice the bandwidth.

When did HBM4 reach mass production?

• SK hynix said on September 12, 2025 that it had completed HBM4 development and readied “mass production for the world’s first time.”
• Samsung said on February 12, 2026 that it had “begun mass production of its industry-leading HBM4 and has shipped commercial products to customers.”
• Micron says it “is in high-volume production of HBM4 36GB 12H” and is sampling a 48 GB, 16-high version.

Samsung expects HBM4E sampling to begin in the second half of 2026. How Samsung and SK hynix Compare in HBM covers the two Korean makers’ market shares and results, and Who Makes What in Memory covers all the memory makers.

Why do AI accelerators need HBM?

Because AI chips are often limited by how fast they can feed data to their compute units, not by the compute itself. Micron gives an example: reasoning models “must evaluate hundreds of intermediate logical steps,” which “requires terabytes of data to flow between main memory and processors each second.”

So each accelerator carries several HBM stacks around the processor. Google’s seventh-generation TPU, Ironwood, has 192 GB of HBM per chip and HBM bandwidth of 7.37 TB/s per chip, according to Google. HBM is used both in GPUs and in custom chips: Micron says HBM4 “works with both GPUs and custom ASICs,” as long as the processor “has the appropriate packaging.” One such packaging puts the processor and its HBM stacks side by side on an interposer: TSMC’s CoWoS, explained in What Is CoWoS?

What does HBM mean for chip stocks?

HBM ties the memory makers’ results to AI spending, because AI accelerators use it. For how accelerator makers’ plans and results reach the memory makers, see Why Nvidia’s Earnings Move Memory Stocks and Custom AI Chips Explained. The Memory map shows SK hynix, Samsung Electronics and Micron side by side with the companies that make the equipment to stack and test HBM.